module LED(flag1,flag2,KEY1,KEY2,LEDR,LEDG,CLOCK_50);
input CLOCK_50;
input flag1,flag2;
input KEY1,KEY2;
output reg [17:0] LEDR,LEDG;
reg [4:0]temp1,temp2;
reg clock_out;
integer i,j,z;
//divide frequency
always @(posedge CLOCK_50) 
begin
if(i==2500000)
begin 
clock_out=~clock_out;
i<=0;
end
else
i<=i+1;
end 

always @(posedge clock_out )
begin
if(flag1==1)
begin
  if(j<5)
   begin
    if (KEY1==0&&KEY2==0) j=5;
   case (temp1)
   5'b00000:LEDR<=18'b001001001001001001;
   5'b00001:LEDR<=18'b010010010010010010;
   5'b00010:LEDR<=18'b011011011011011011;
   5'b00011:LEDR<=18'b100100100100100100;
   5'b00100:LEDR<=18'b101101101101101101;
   5'b00101:LEDR<=18'b110110110110110110;
   5'b00110:LEDR<=18'b111111111111111111;
   5'b00111:begin LEDR<=18'b000000000000000000;j=j+1;end
    endcase
      if(temp1==5'b00111)
      temp1<=5'b00000;
      else
      temp1<=temp1+1'b1;
   end
   
else LEDR<=18'b000000000000000000;
end
else j=0;

if(flag2==1)
begin
  if(z<5)
   begin
   case (temp2)
   5'b00000:LEDG=8'b01010101;
   5'b00001:LEDG=8'b00000000;
   5'b00010:LEDG=8'b10101010;
   5'b00011:LEDG=8'b00000000;
   5'b00100:LEDG=8'b11111111;
   5'b00101:LEDG=8'b00000000;
   5'b00110:LEDG=8'b10101010;
   5'b00111:begin LEDG=8'b01010101;z=z+1;end
   endcase
      if(temp2==5'b00111)
      temp2<=5'b00000;
      else
      temp2<=temp2+1'b1;
   end
else LEDG<=8'b00000000;
end
else z=0;
end

endmodule
